The present invention relates to a PLL (Phase Locked Loop) circuit and more particularly to a PLL circuit including a frequency difference memorizing portion generally referred to as a secondary loop.
A PLL circuit produces an error signal representative of a difference between the phase of an input frequency and the phase of a frequency output from a VCO (Voltage Controlled Oscillator). The PLL circuit controls the oscillation frequency of the VCO by feedback control such that the above error signal decreases to substantially zero. While so-called PI (Proportional and Integral) control and PDI (Proportional, Differential and Integral) control have customarily been used to improve a feedback control characteristic, PI control is usually applied to the PLL circuit. The PLL circuit with the PI control scheme controls the oscillation frequency of the VCO with the sum of a voltage proportional to the error signal and a voltage proportional to the time integral of the error signal.
When the PLL circuit is built in a communication apparatus, particularly in a synchronous multiplexing device called SDH, it is necessary to reduce a pull-in time. Also, when a clock source for synchronization, i.e., the phase of the input signal frequency is lost, a control voltage corresponding to a difference between the input signal frequency and the self-running frequency of the VCO must be memorized as the output voltage of an integrator so as to maintain the output frequency of the VCO accurate despite the absence of the clock source (so-called holdover).
However, the conventional PLL circuit cannot achieve both of the short pull-in time and stable holdover at the same time.
Technologies relating to the present invention are disclosed in, e.g., Japanese Patent Laid-Open Publication Nos. 2-280414, 6-252746, 7-193497 and 8-84071, and Japanese Patent No. 2,527,010.